Proposal to build a programming interface for easy verification of RISC-V Debug Specification.

“The Debug Module is controlled via register accesses to its DMI address space”
- RISC-V Debug spec.

This makes it a bit tedious to read/write many registers to test one scenario.

The proposed interface will be able to abstract the debug module registers as data structures. This will allow the programmer to easily read/write/compare attributes using only their names. One would be able to assign values to these structure variables and the assigned values would be randomizable or the result of a function. Using loops, conditional statements and functional programming support, one could run iterated tests on one or a combination of registers. The most common test scenarios will be provided as built-in functions. The interface will provide integration to any c/c++ software that is used to communicate with the debug module.

Users will be able to test complex scenarios with a few lines of code and almost zero computation of complex register values. Furthermore, there will be a configurable provision to randomize the number of times and the points at which a particular scenario is executed.

This interface aims to make testing the specification easy and infinitely scalable.