Barath Kumar Ramaswami is a Lead Application Engineer at Cadence Design Systems in Santa Clara, California, specializing in hardware emulation architecture, FPGA-based prototyping, and pre-silicon validation for hyperscale System-on-Chip (SoC) designs. With over a decade of experience spanning ASIC, VLSI, and FPGA engineering, he has led the functional validation and regression testing of the emulation industry's premier 16-rack enterprise hardware computing platform, managing runtime routines for customer designs scaling up to 43 billion logic gates. Barath has architected autonomous, LLM-backed multi-agent frameworks, leveraging CrewAI, Model Context Protocol (MCP), and closed-loop regression pipelines, to automate emulation operations that traditionally required extensive manual engineering effort, coordinating technical task forces across Shanghai, India, and North America. His pre-silicon risk mitigation work includes isolating a catastrophic layout defect in a client's flat-netlist hyperscaler ASIC during DFT emulation, saving the client millions in potential fabrication delays. Barath's published research on agentic AI frameworks for multi-FPGA partitioning and enterprise emulation mapping has demonstrated a 44% reduction in inter-FPGA signal cuts, a 4.5x increase in emulation execution frequency, and an 85% reduction in VIP integration time. He holds an M.S. in Computer Engineering (VLSI and Integrated Circuit Systems) from the University of California, Santa Barbara. Barath's speaking engagements focus on agentic AI applications in EDA workflows, high-speed protocol integration (PCIe Gen6, HBM3/4), and the future of autonomous pre-silicon validation infrastructure for next-generation cloud and AI-optimized SoC platforms.