Jayanth Noonety is a systems power engineer specializing in Linux kernel engineering, system-on-chip power architecture, and low-level performance optimization for mobile computing platforms. His work centers on the trade-off that governs every modern processor: a device saves power by spending time in low-power states and feels responsive by leaving them quickly, and transition latency sets the price of both.

He works across Linux kernel subsystems including CPU idle and frequency management, energy-aware scheduling, device drivers, DMA engines, CPU latency constraints, and device tree platform configuration. His engineering contributions include reducing deep CPU sleep-state entry latency by over 80% on a flagship mobile SoC, cutting always-on processor wake latency from 83 ms to 10 ms, halving system suspend latency, and recovering deep sleep residency from 47.7% to 78.1% on a platform that had regressed against its predecessor. He authored the C-state breakeven characterization methodology adopted as the technical standard across three subsequent flagship processor generations, and built the automation that compressed each characterization pass from months into weeks.

Previously he worked on embedded mobile modem platforms, developing low-power 5G Layer 1 software, serving as global point of contact for six thermal mitigation features across sub-6GHz and mmWave subsystems, optimizing modem clock infrastructure, and resolving more than 100 production issues involving concurrency, memory corruption, and real-time operating systems. He also built automated validation pipelines for protocol state machines and low-level driver components.

His technical interests include real-time Linux scheduling, eBPF-based kernel telemetry, secure trusted execution environments, high-performance packet processing, and low-power audio driver architecture.

Jayanth holds a Master of Science in Computer Science from Arizona State University and a Bachelor of Technology in Computer Engineering from the Indian Institute of Information Technology Allahabad. He was a global finalist at the CSAW Capture the Flag World Finals at NYU Tandon School of Engineering, and has twice received corporate peer recognition for power engineering contributions on production silicon.