Kavya Gaddipati is a Custom Analog/Mixed-Signal Layout Engineer with over five years of professional experience designing and implementing advanced IC layouts for cutting-edge semiconductor technologies. Currently based in Austin, TX, she works at NVIDIA as a Senior Mask Design Engineer, where she is involved in physical design and mask layout development for advanced semiconductor processes.
Kavya specializes in high-precision analog layouts, including LVDS transmitters, ESD protection structures, power supervisor IPs, and current viewing circuitry. Her expertise spans advanced matching techniques such as common centroid, interdigitation, proximity matching, and dummy insertion, enabling low-noise, low-power designs with minimized parasitic RC. She is also proficient in physical verification, routinely resolving complex DRC/LVS issues, antenna effects, latch-up, and IR drop concerns using industry-leading tools such as Cadence Virtuoso, Calibre, Synopsys ICV, Redhawk, and Totem.
Before her current role, Kavya contributed to Intel’s advanced node technologies, including work on custom IO buffer IP development for 5G telecom applications, where she performed placement, routing, and yield enhancement across hierarchical design flows using Cadence Innovus and Nanoroute. She also worked on FinFET-based digital block layouts, including clock dividers, decoders, and glitch filters.
Kavya holds a Master of Science in Electrical Engineering from Arizona State University's Ira A. Fulton Schools of Engineering and a Bachelor's degree in Electronics Engineering from Anna University, India. Her strong academic foundation, combined with her hands-on industry experience, makes her a versatile and highly capable IC layout professional.