Manoj Murali
University of Florida
San Jose, California, United States
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Manoj Murali is a seasoned SoC Physical Design and Timing Engineer with over a decade of experience in leading-edge semiconductor design and verification. Currently at Apple Inc., he plays a pivotal role in full-chip integration and timing closure for high-performance SoCs, specializing in clocking uncertainty modeling, scan shift-capture timing, IO timing closure, and low-power optimization. As a project co-lead, he coordinates cross-functional teams to ensure sign-off closure across diverse technology nodes.
Previously, Manoj contributed to Intel Corporation as a SoC Design Engineer and Technical Intern, where he led full-chip clock network design, timing analysis, and signoff strategies for lower technology nodes. He began his career at Open-Silicon, focusing on static timing analysis, synthesis, and power analysis for complex hierarchical ASIC designs.
Manoj holds a Master’s degree in Electrical and Computer Engineering from the University of Florida and a Bachelor’s in Electronics and Communication Engineering from Model Engineering College. His technical arsenal includes tools like Tempus, PrimeTime, and RTL Compiler, with programming expertise in C, Python, and scripting languages like TCL and Perl.
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