Rajesh Arsid is a highly accomplished Principal Engineer in ASIC Physical Design, with extensive experience in the semiconductor industry and a strong track record of delivering complex, high-performance integrated circuit solutions. At Synopsys Inc., he plays a key role in the development of cutting-edge PCIe subsystem architectures, contributing to multiple generations of PCIe and CXL designs that power advanced computing and AI applications. His work has supported major global technology leaders in achieving critical product milestones.
Rajesh's technical strengths encompass the entire ASIC physical design flow, from floor planning and clock tree synthesis to power grid architecture, signal integrity, and final tape-out. He brings deep expertise in multi-voltage and low-power design strategies across advanced FinFET and legacy technology nodes. His collaborative leadership style and global team coordination capabilities have enabled the successful execution of complex SoC programs under tight schedules.
Throughout his career, Rajesh has contributed to the development of a diverse range of technologies, including 1.6T Ethernet controller, Mult-Core Processor, Storage controllers, GNSS receivers, (RAID)-on-chip storage and fiber-to-the-home SoCs. His ability to drive innovation, optimize design flow methodologies, and resolve critical challenges has earned him numerous accolades for execution excellence, innovation, and customer success.
Rajesh holds a Master of Science in Electronics and Communication from Napier Edinburgh University in the United Kingdom and a Bachelor of Engineering from Bangalore University in India. He is also a certified IC Layout Design Engineer through Cadence Design Systems. His commitment to continuous learning, process improvement, and technical mentorship has made him a valuable contributor to the semiconductor design community.