Ramalinga Reddy Kotapati is a seasoned VLSI ASIC Physical Design Engineer with over 15 years of experience specializing in High-Performance Computing (HPC) and Graphics Processing Units (GPU) across advanced semiconductor technology nodes. With a proven track record of delivering over 30 successful tape-outs, he has contributed to cutting-edge projects at process nodes ranging from Intel 14A/18A to TSMC 7nm and 16FF.
Currently a Technical Lead at Intel Corporation, Ramalinga Reddy spearheads physical design implementations for advanced semiconductor technologies, including FinFET architectures and high-performance designs for CPUs, GPUs, and data center applications. His expertise includes synthesis, place and route (P&R), static timing analysis (STA), engineering change orders (ECO), and advanced EDA tools like INNOVUS and Fusion Compiler.
Previously, he held pivotal roles at Cypress Semiconductor (Infineon Technologies), AMD, and Aricent Technologies, leading complex chip design processes. At Cypress, he played a key role in achieving consistent Power, Performance, and Area (PPA) improvements, completing full chip design closures for PSoC projects and advancing production timelines significantly.
Ramalinga Reddy has extensive experience in low-power design methodologies, floor planning, clock tree synthesis, IR drop mitigation, and package ARC cleanup. He has mentored numerous engineering teams, fostering innovation and collaboration while ensuring adherence to stringent project deadlines.
A Master's graduate in VLSI Design from JNTU Hyderabad, Ramalinga Reddy continues to drive advancements in semiconductor technology, focusing on achieving optimal PPA metrics and streamlining physical design workflows for next-generation chips.