Rambabu Mandalapu is an accomplished Physical Design Engineer with over 15 years of experience in advanced SoC and IP-level physical implementation. He has executed multi-million gate designs across technology nodes ranging from 45nm down to 3nm, incorporating ARM cores, DSPs, and complex low-power architectures. He brings deep expertise across the full RTL-to-GDSII flow, including synthesis, floorplanning, placement, clock tree synthesis, routing, timing closure, signoff, and tapeout.
Currently serving as a Physical Design Domain Lead at a leading semiconductor company in Cupertino, California, Rambabu leads physical design efforts for multiple Power Management Unit (PMU) chips at both block and top levels. He is responsible for physical signoff and tapeout to TSMC, ensuring manufacturability and quality, and acts as the primary physical design contact for TSMC, coordinating tapeout milestones and technical readiness. His role involves close collaboration with analog design, system integration, RTL, and packaging teams to resolve integration and constraint challenges while driving timing, power, and physical verification convergence across complex low-power domains.
Previously, Rambabu served as Engineering Manager, Physical Design at Calsoft Labs, where he managed top-level and block-level PnR efforts for advanced-node test chips and delivered high-performance partitions and subsystems for clients including Qualcomm and Samsung. He also contributed to multiple partitions at Microsoft by supporting PnR closure and sign-off. Earlier, at UST Global, he led hard macro implementation and full-chip place and route for networking SoCs at Microsemi. At Qualcomm India, he served as a subsystem physical design lead for modem blocks in MSM chipsets, executing complete physical design cycles across multiple technology nodes.
Rambabu began his career in physical design at CMC India and completed an internship at Intel, where he contributed to the Ivy Bridge processor during his M.Tech program. He holds an M.Tech in VLSI System Design from the National Institute of Technology (NIT), Warangal, and a B.Tech in Electronics & Communication Engineering from Acharya Nagarjuna University.
With extensive experience across advanced process nodes and a consistent record of delivering production-ready silicon, Rambabu brings strong technical expertise, cross-functional collaboration, and execution excellence to complex semiconductor programs.