The SONiC ecosystem is rapidly expanding from the data center to the edge. However, a critical gap remains in achieving deterministic, carrier-grade failure detection required for these deployments. Pure software BFD implementations often suffer from CPU jitter and control-plane contention, making sub-10ms convergence unreliable during high-load incidents.

We have addressed this by implementing true hardware-accelerated BFD on the Marvell platforms. We developed custom firmware running on the CM3 co-processor to manage the full BFD state machine. We also integrated this machine with SONiC and want to share this architecture with the community.

This architecture overcomes the "single-interval" limitations of standard traffic generators, delivering up to 64 concurrent sessions with intervals down to 3ms. Join us to see how offloading "heartbeats" to the CM3 guarantees stability and allows SONiC to meet strict SLAs in L3 networks.