AI workloads are exploding, and running CPUs, GPUs, and TPUs together efficiently is now critical for performance, energy, and cost in HPC systems.

In this talk, I’ll share my experience with co-scheduling MIMD CPUs, SIMT GPUs, and systolic-array TPUs, showing how differences in execution models, memory hierarchies (NUMA, HBM, on-chip SRAM), and programming abstractions shape workload partitioning, data movement, and scheduling granularity. I’ll cover static, semi-static, and dynamic strategies and highlight their impact on performance portability, energy efficiency, and cost.

Instead of isolated benchmarks, I focus on end-to-end system behavior, emphasizing performance portability, energy-aware scheduling, and cost-efficient use of open HPC software stacks effectively. You will leave with actionable insights to co-schedule heterogeneous workloads smarter, CPUs, GPUs, and TPUs effectively, unlocking higher performance, lower energy use, and cost savings for both AI and HPC workloads.