In semiconductor manufacturing R&D environments, product routes are initially sketched using a reference process flow, while their effective realization unfolds progressively during execution through local decisions, lot filiations, and device-team holds, which can be assimilated to slowdown and hold-induced interruptions. In this paper, we propose a predictive modeling approach to anticipate such slowdown regions along R&D routes. This approach corresponds to a static view, in which at the beginning of lot processing, it estimates slowdown risks over the whole route horizon.