Sharvani Mukkala is a semiconductor verification engineer with over nine years of experience in functional and post-silicon verification, currently serving as a SMTS Silicon Design Verification Engineer at AMD in Austin, Texas. She specializes in digital low-power IP verification, leading the full verification lifecycle, from test plan development and UVM infrastructure design to coverage closure, for IPs including digital low-dropout regulators, power gating, droop detection, and temperature sensors. Her career spans AMD and Intel, where she built deep expertise in PCIe PHY physical-layer verification across multiple process generations. Sharvani has been recognized with department-level awards at both companies: at AMD, for delivering a low-power IP on an unstable N2 node within a single quarter; and at Intel, for root-causing a chip-killer bug on a PCIe Gen5 test chip and for leading PCIe PHY bring-up on the RocketLake platform while supporting more than ten firmware releases on an accelerated schedule. She has driven measurable engineering efficiency gains, including cutting co-simulation runtimes in half (from 18-24 hours down to 8-10 hours) through tool and methodology optimization. Beyond technical execution, Sharvani mentors junior and staff-level engineers, having ramped up new hires and interns on complex verification environments. She holds an MS in Electrical Engineering from Arizona State University and a BE in Electronics & Communication Engineering from Osmania University. Her speaking engagements focus on low-power verification methodologies and practical lessons from high-volume semiconductor manufacturing.