Sheetal Kaul is a seasoned Senior SOC Design Engineer at Intel Corporation with over 10 years of specialized experience in digital IP and System-on-Chip (SOC) design. Based in Hillsboro, Oregon, she has established herself as a leading expert in low-power design technologies and digital IC development.
Sheetal holds a Master of Science in Electrical & Computer Engineering from Portland State University (2015), specializing in Digital IC Design, and a Bachelor of Engineering in Electronics & Communication Engineering from the University of Jammu, India (2006). Her strong academic foundation, reflected in her 3.78 GPA, has served as the cornerstone for her distinguished career in semiconductor design.
At Intel Corporation, where she has progressed through multiple engineering roles since 2015, Sheetal has made significant contributions to power optimization and SOC integration. Her expertise encompasses developing low-power features including Dynamic Frequency Scaling (DFS), Dynamic Voltage Scaling (DVS), and Dynamic Voltage and Frequency Scaling (DVFS) to improve Power, Performance, and Area (PPA) metrics. She has successfully designed FPGA acceleration platforms, implemented APB protocol specifications, and managed comprehensive quality flows including Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and Unified Power Format (UPF).
Her technical proficiency spans multiple programming languages including Verilog, System Verilog, C, TCL, and Perl, along with industry-standard tools such as VCS, Design Compiler, and Quartus. Sheetal's role as a partition owner has given her end-to-end responsibility for backend flows, from synthesis through place and route to timing convergence.
Prior to her semiconductor career, Sheetal gained valuable experience in software development across the telecom domain, working with prestigious organizations including Nokia, Renesas Mobile Corporation, and HSBC Global Technology. This diverse background has enriched her understanding of system-level design and cross-functional collaboration.
Sheetal is an active contributor to the engineering community, holding senior memberships in IEEE and fellowships in multiple professional organizations including IETE and NIPES. She has authored several publications on low-power design techniques and telemedicine applications, demonstrating her commitment to advancing the field through research and knowledge sharing.