Sudeep Joshi is a CPU enthusiast working at MIPS-Technology in Bengaluru, India, as a Design Verification Engineer with 1.5 years of experience. After graduating with an Electronics and Communication degree in 2024, he developed a 5-stage pipelined RISC-V CPU supporting RV32I for his final-year project, igniting his passion for RISC-V. At MIPS, he contributes to building a robust RISC-V CPU ecosystem.