Vishvam Madishetti is a Silicon Design Engineer with more than 17 years of experience in advanced semiconductor technology and physical design engineering. His expertise spans leading-edge process nodes, including TSMC N2P, N2, N3, FinFET, and Gate-All-Around (GAA) architectures, with a strong focus on delivering high-performance, scalable silicon solutions for compute-intensive applications.
Currently, Vishvam serves as a Senior Member of Technical Staff at AMD, where he leads physical design initiatives for advanced GPU and AI compute products. He has contributed to the development of AMD Instinct MI and RDNA GPU programs, driving subsystem implementation, place-and-route, timing closure, power optimization, and performance, power, and area (PPA) exploration for next-generation AI training and inference platforms. His work includes leading physical design efforts on TSMC’s N2 process technology and collaborating with EDA vendors to optimize design methodologies for advanced technology nodes.
Before AMD, Vishvam worked as a Principal Physical Design Engineer at TSMC, where he played a key role in the implementation and closure of one of the industry's early subsystems on the TSMC N3 (3nm) technology node. His responsibilities included advanced floorplanning, clock tree synthesis, timing closure, power integrity analysis, low-power verification, and full physical signoff. He also contributed to the development of hybrid standard-cell methodologies and collaborated with EDA vendors to advance implementation and signoff techniques for 3nm technologies.
Earlier in his career, Vishvam served as a Member of Technical Staff at SoCtronics, leading Design Technology Co-Optimization (DTCO) initiatives across GlobalFoundries FinFET and FD-SOI platforms. He worked on standard cell library development, SRAM and physical design optimization, track-specific design methodologies, and PPA benchmarking to support automotive, 5G, and IoT semiconductor applications.
Throughout his career, Vishvam has gained experience across multiple organizations, including AMD, TSMC, SoCtronics, Apple, Intel, Texas Instruments, ST Ericsson, Cypress, Synapse, and others, contributing to a wide range of semiconductor product domains. His technical expertise encompasses physical design methodologies such as place-and-route, timing closure, power optimization, and signoff verification, supported by extensive experience with industry-standard EDA tools including Synopsys Fusion Compiler, PrimeTime, Design Compiler, Cadence Innovus, Genus, Voltus, Mentor Graphics Calibre, and related platforms.
Vishvam holds a Master of Science in Industrial Electronics from Bharathidasan University, a Bachelor of Science in Electronics from Kakatiya University, and a Diploma in Physical Design from TTM India.