Alok Gupta
Principal Engineer, AMD. GPU architecture, performance modelling and system software for embedded AI.
Actions
Alok Gupta is a Principal Engineer at AMD, where he owns graphics and compute system software for AMD's embedded platforms. He works at the point where architecture, performance and customer enablement converge, turning silicon capability into software that ships at scale.
Across more than two decades in AI accelerators, GPUs and system-on-chip platforms, Alok has driven the adoption of GPU software stacks for next-generation edge compute, spanning graphics, compute, performance modelling and simulation, and the Physical AI workloads now being built on top of them. He still writes the kernels and runs the benchmarks behind his talks. Before AMD, he built machine learning systems, graphics pipelines and silicon performance models at NVIDIA, Intel and Synopsys, giving him a rare view of the same problem from three different architectures.
He holds advanced degrees in Computer Science and Machine Learning from the University of Texas at Austin and Liverpool John Moores University, and pairs deep systems engineering with the product and strategic judgment to decide which problems are worth solving.
Porting Parallel Programming Code With AI Agents: Surviving the Long Tail
Every team that ports GPU code underestimates it, and the underestimate always lands in the same place. The mechanical translation is largely solved. The expense is the long tail: kernels that compile and run and produce almost the right answer, kernels that are correct but several times slower, and kernels that fail only on one input shape. That tail is where months go.
This talk presents a method for putting an LLM agent to work on that tail without trusting it. The centerpiece is the verification harness, not the model. Numerical equivalence gates with tolerances chosen per operation. Shape and dtype sweeps that catch the cases a human reviewer skips. Performance regression gates so a successful port cannot quietly be a slowdown. We walk through a real migration of vision and control kernels to HIP on an embedded GPU, categorize every failure the agent produced, and are specific about which categories it handled reliably, which it handled with review, and which it got wrong in ways that looked plausible. Attendees get a harness design they can rebuild
Beyond TOPS: What Actually Determines Physical AI Performance at the Edge
Nearly every embedded AI processor is marketed with a TOPS number that predicts almost nothing about whether a Physical AI system meets its control deadline. The model may be fast, but the loop also runs stages no framework operator matches: turning depth into a grasp candidate, locating an object under uncooperative lighting, maintaining an occupancy grid, deciding from tactile signal whether the gripper has closed. We follow one such loop on a processor where CPU, integrated GPU and NPU share one memory pool. We show where each stage should run, what handoffs cost, how access patterns, occupancy and local memory decide whether a stage fits its budget, and how to benchmark the deployed loop instead of flattering the silicon. A fast wrong stage is worse than a slow right one, so we cover verification and our own measurement mistakes. The one-page checklist is worth taking home.
Architecture Apocalypse: The Memory Model Behind Fast Inference for Physical AI
Most edge AI software is still written as if the accelerator lives on the other side of a bus. Tensors get staged, copied, and copied back. Buffers get duplicated because two frameworks each insist on owning them. The memory budget gets split into a CPU half and a GPU half before a single model is loaded. On a part where the CPU, GPU and NPU share one physical memory pool, those habits are pure overhead, and they are baked into most of the stacks people port over from discrete-GPU development. This session is a practical guide to the memory model that Physical AI workloads need on a unified-memory edge SoC, using ROCm on an integrated GPU as the working example. It covers where zero-copy actually happens versus where the runtime quietly inserts a copy, how to allocate so that a multi-gigabyte model and a live camera pipeline coexist without fragmentation, what the NPU and the iGPU can and cannot hand to each other, and how to tell a real memory win from a measurement artifact. We show a 7B-class VLM, a perception stack and a control policy co-resident in one shared pool, with measured results.
Please note that Sessionize is not responsible for the accuracy or validity of the data provided by speakers. If you suspect this profile to be fake or spam, please let us know.
Jump to top